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oki semiconductor fedl66525-02 issue date: july 19, 2002 ml66525 family 16-bit microcontroller 1/27 general description the ml66525 family devices are high-performance 16-bit cmos microcontrollers that utilize the nx-8/500s, oki?s proprietary cpu core. data from a personal computer with a usb connector can be automatically, quickly written or read to and from nand type flash memory via usb i/f and nand flash memory i/f. the ml66525 family devices support clock gear functions, a sub-clock and halt/stop mode, which are suitable for low power applications. the ml66525 family devices are provide d with interfaces to external devices such as a 4-channel multi-functional serial interface with internal 32-byte fifo and a high-speed bus interface that has separate address and data buses and does not require external address latches. a wide variety of internal multi-functional timers enab le various timing controls such as periodic and timed measurements. with a 16-bit cpu core that enables high-speed arithmetic computations and a variety of bit processing functions, these general-purpose microcontrollers are optimally suited for digital audio devices such as mp3 players, voice recorders, handy games, and pc peripheral control systems (to control devices that can be connected to usb and store data into memory). the ml66525 family devices also include the flash rom version device (ml66q525b) that is programmable with a single 3 v power supply (2.4 to 3.6 v). [ note ] ml66525a/ml66q525a are supplied as stock lasts. applications ? small-sized handy systems that require usb control and storage control (digital audio players, etc) ? pc peripheral control systems ordering information order code or product name package remark ML66525B-XXTB *1 mask rom version (2.4 to 3.6 v) ml66q525b-ntb *2 100-pin plastic tqfp (tqfp100-p-1414-0.50-k) ml66525b flash rom version (2.4 to 3.6 v) ml66525b-xxla *1 ml66525b bga package version (2.4 to 3.6 v) ml66q525b-nla *2 144-pin plastic lfbga (p-lfbga144-1111-0.80) ml66q525b bga package version (2.4 to 3.6 v) *1 : the ?xx? of ?-xx? stands for the code number. *2 : the ?n? of ?-n? stands for the flash rom blank version. when oki programs and ship the flash rom, t he part number is changed from ??n? to ??xx? (code number ) , for example, ml66q525b-999tb.
fedl66525-02 oki semiconductor ml66525 family 2/27 features parameter ml66525b o p eratin g tem p erature ?30 to +70c power supply voltage/ v dd = 2.4 to 3.6 v / f = 24 mhz maximum operating frequency 83 nsec @ 24 mhz minimum instruction execution time 61 2ch 8-bit auto-reload timer 1ch 8-bit auto-reload timer 8-bit auto-reload timer ( also functions as watchdo g timer ) 1ch watch timer 1ch timers 8-bit pwm 2ch ( can also be used as 16-bit pwm 1ch ) s y nchronous ( with 32-b y te fifo ) 1ch s y nchronous ( shift re g ister t yp e ) 1ch serial port s y nchronous/uart 2ch a/d converter 10-bit 4ch non-maskable 1ch external interrupts maskable 6ch com p liant with usb s p ec. version 1.1 hi g h-s p eed transfer at 12 mb p s internal pll ( x2 , x3 , x4 ) -> 48 mhz internal transceiver vbus detection circuit ( connection to usb host : detect/non-detect ) bus p ower available ep0 ( in 32 b y tes, out 32 b y tes ) , control transfer ep1 ( 64 b y tes 2 ) , bulk/interru p t transfer ep2 ( 64 b y tes 2 ) , bulk/interru p t transfer ep3 ( 32 b y tes ) , bulk/interru p t transfer ep4 ( 64 b y tes 2 ) , bulk/isochronous/interru p t transfer ep5 ( 64 b y tes 2 ) , bulk/isochronous/interru p t transfer usb control automatic, hi g h-s p eed data transfer ecc circuit nand flash memory control automatic, hi g h-s p eed 512-b y te data transfer interru p t p riorit y 3 levels external bus interface ( se p arate address and data buses ) dual clocks function clock g ear function others different p ower available amon g usb, cpu core, and i/o p ort flash rom version ml66q525b
fedl66525-02 oki semiconductor ml66525 family 3/27 functional description 1. high-performance cpu the ml66525 family devices include the high-performance cpu, powerful bit manipulation instruction set, a variety of symmetrical addressing modes, and rom window function, and also supports the best-optimized c compiler. 2. a variety of power saving modes attaching a 32.768-khz crystal produces a real time clock signal from the internal clock timer. a single clock can be used in place of dual clocks. switching the cpu clock to the dual clocks (1/2 or 1/ 4 of the main clock) enable s operation in a low power consumption mode. the clock gear function allows a 1/2 or 1/4 clock signal of the main clock to be selected as the cpu operating clock. the ml66525 family devices are provided with a wide range of standby control functions such as the stop mode that stops the oscillation circuit, the quick restart stop mode that stops the cpu and peripherals while the oscillation circuit is operating, and the halt mode that shuts down the cpu while peripherals are operating. 3. usb control the family include usb controller which compliant with usb specification version 1.1 and can be transferred data with 12mbps circuit. also, usb controller have 6 kinds of endpoint and apply for control/bulk/isochronous/interrupt transfer. with nand flash memory control circuit, high speed data transfer is possible. 4. nand flash memory control the family include control circuit of nand flash memo ry. automatically data read from and write to outside nand flash memory with 528 byte. also, include ecc circuit which detect data error and correct data error. 5. ml66q525b with flash memory progr ammable with single power supply in addition to mask rom version devices, the ml66525 family devices include the ml66q525b with internal 128 kbytes of flash memory that can be programmed with a single power supply. the flash memory of the ml66q525b can be programmed with a low power supply (2.4 to 3.6 v) using the internal voltage booster circuit. 6. multifunctional, high-precisi on analog-to-digital converter the family devices include a high-pr ecision 10-bit analog-to-di gital converter with four channels and are ideal for such analog control functions as processing audio signals, processing sensor inputs, detecting key switch states, and controlling battery use in portable equipment. each channel has its own result register readily accessible from the software.
fedl66525-02 oki semiconductor ml66525 family 4/27 7. multifunctional pwm the family devices support both 8- and 16-bit pwm operations. choosing between the time base counter output and the overflow from an 8-bit auto-reload tim e as the pwm counter cloc k source provides a great number of possibilities over a broad frequency range. the 16-bit pwm configuration supports a high-speed synchronization mode that generates a high-precision output signal with less ripple suitable for digital-to-analog applications. 8. programmable pull-up resistors building the pull-up resistors into the chip contributes overall design compactness. making them programmable on a per-bit basis allows complete flexibility in circuit board layout and system design. these programmable pull-up resistors are availabl e for all i/o pins except ports that have specific functions such as oscillator connection pins. 9. high-speed bus interface the interface to external devices us es separate data and address buses. this arrangement permits a rapid bus access for controlling the system from the microcontroller. 10. a variety of external interrupts there are a total of seven interrupt channels for use in communicating with external devices; six channels for maskable interrupts and one channel for non-maskable interrupts.
fedl66525-02 oki semiconductor ml66525 family 5/27 block diagram resn osc0 osc1n xt0 xt1n ram 4kbyte rom 128 kbyte bus port control port control 8-bit timer4/brg sio1 (uart/sync) 8-bit timer6/wdt tbc interrupt rxd1 txd1 rxc1 txc1 exint0 to exint4 ssp psw lrb pc dsr tsr csr control registers system control memory control pointing registers local re g isters instruction decoder cpu core ean psenn rdn wrn d0 to d7 a0 to a19 p0 (8 bit) p1 (8 bit) p2 (4 bit) p3 (3 bit) p4 (8 bit) p6 (4 bit) p7 (2 bit) p8 (4 bit) p9 (1 bit) p10 (6 bit) p12 (4 bit) p13 (2 bit) p15 (4 bit) p20 (8 bit) p21 (5 bit) alu alu control acc 16-bit timer7 8-bit timer9 nmi exint8/9 16-bit timer0 8-bit timer3/brg sio6 (uart/sync) rxd6 txd6 rxc6 txc6 sio3 (sync) sioi3 sioo3 siock3 8-bit timer5/brg sio4 (32-byte fifo sync ) sioi4 sioo4 siock4 8-bit pwm0 8-bit pwm1 pwmout0 pwmout1 10-bit a/d converter vref agnd ai0 to ai3 rtc + 2kb y te usb (compliant with ver1.1) puctl d+/d? transfer ram (512 bytes 4 banks) dma (usb ? transfer ram) flash media control dma (media ? transfer ram ) fd0 to fd7 frdn fwrn fcle fale frb also functions as transfer ram usb dma transfer flash me di a dma transfer bus
fedl66525-02 oki semiconductor ml66525 family 6/27 pin configuration (top view) vbus p9_0/vbusin p6_0/exint0 p6_1/exint1 p6_2/exint2 p6_3/exint3 p7_6/pwm0out p7_7/pwm1out flamod p8_0/rxd1 p8_1/txd1 p8_2/rxc1 p8_3/txc1 gnd v dd _io p10_0/siock3 p10_1/sioi3 p10_2/sioo3 p10_3/siock4 p10_4/sioo4 p10_5/sioi4 p15_0/rxd6 p15_1/txd6 p15_2/rxc6 p15_3/txc6 p2_3/a19 p2_2/a18 p2_1/a17 p2_0/a16 v tm p1_7/a15 p1_6/a14 p1_5/a13 p1_4/a12 p1_3/a11 p1_2/a10 p1_1/a9 p1_0/a8 p4_7/a7 p4_6/a6 p4_5/a5 p4_4/a4 p4_3/a3 p4_2/a2 p4_1/a1 p4_0/a0 v dd _core gnd v dd _io v dd _core resn nmi ean v dd _io xt0 xt1n gnd test osc0 osc1n v dd _io p13_0/exint8 p13_1/exint9 p0_0/d0 p0_1/d1 p0_2/d2 p0_3/d3 p0_4/d4 p0_5/d5 p0_6/d6 p0_7/d7 p3_1/psenn p3_2/rdn p3_3/wrn puctl gnd p20_7/fd7 p20_6/fd6 p20_5/fd5 p20_4/fd4 p20_3/fd3 p20_2/fd2 p20_1/fd1 p20_0/fd0 v dd _io gnd p21_4/frb p21_3/fale p21_2/fcle p21_1/fwrn p21_0/frdn agnd ai3/p12_3 ai2/p12_2 ai1/p12_1 ai0/p12_0 v ref d+ d? 80 85 90 95 100 1 5 10 15 20 25 75 70 65 60 55 50 45 40 35 30 v dd _core 100-pin plastic tqfp a symbol with ?n? suffixed indicates an active low pin.
fedl66525-02 oki semiconductor ml66525 family 7/27 pin configuration (top view) nc v dd _io p3_2/ rdn nc p0_5/ d5 p0_3/ d3 p13_1/ exint9 osc0 gnd xt0 nmi v dd _ core nc n gnd p3_3/ wrn p3_1/ psenn p0_4/ d4 p0_2/ d2 p0_1/ d1 v dd _io osc1n test xt1n v dd _io p15.2/ rxc6 p15_3/ txc6 m p4_0/ a0 nc v dd _ core p0_7/ d7 p0_6/ d6 p0_0/ d0 p13_0/ exint8 nc nc ean resn p15_0/ rxd6 p15_1/ txd6 l p4_2/ a2 nc p4_1/ a1 nc nc nc nc nc nc nc p10_4/ sioo4 p10_2/ sioo3 p10_5/ sioi4 k p4_4/ a4 p4_5/ a5 p4_3/ a3 nc nc p10_3/ siock4 nc nc j p4_6/ a6 p4_7/ a7 p1_0/ a8 nc nc v dd _io p10_0/ siock3 p10_1/ sioi3 h nc p1_1/ a9 p1_2/ a10 nc nc p8_3/ txc1 p8_2/ rxc1 gnd g p1_5/ a13 p1_4/ a12 p1_3/ a11 nc nc p8_1/ txd1 p8_0/ rxd1 nc f nc nc p1_7/ a15 nc nc p7_6/ pwm0o ut flamo d p7_7/ pwm1o ut e nc p1_6/ a14 v tm nc nc nc nc nc nc nc p6_2/ exint2 nc p6_3/ exint3 d p2_1/ a17 p2_0/ a16 v ref p12_1/ ai1 p12_3/ ai3 p21_4/ frb v dd _io p20_1/ fd1 p20_7/ fd7 nc p6_0/ exint0 nc p6_1/ exint1 c p2_3/ a19 p2_2/ a18 nc agnd p21_1/ fwrn p21_3/ fale gnd p20_2/ fd2 p20_3/ fd3 p20_5/ fd5 puctl d- p9_0/ vbusin b nc v dd _ core p12_0/ ai0 p12_2/ ai2 p21_0/ frdn p21_2 /fcle p20_0 /fd0 p20_4/ fd4 p20_6/ fd6 gnd d+ vbus nc a 13 12 11 10 9 8 7 6 5 4 3 2 1 144-pin plastic lfbga a symbol with ?n? suffixed i ndicates an active low pin. [note] don?t connect nc pins with others.
fedl66525-02 oki semiconductor ml66525 family 8/27 pin descriptions in the type column, ?i? indicates an input pin, ?o? indicates an output pin, and ?i/o? indicates an i/o pin. a symbol with ?n? suffixed i ndicates an active low pin. description classification symbol type primary function type secondary function p0_0/d0 to p0_7/d7 i/o 8-bit i/o port pull-up resistors can be specified for each bit. i/o external memory access data i/o port p1_0/a8 to p1_7/a15 i/o 8-bit i/o port pull-up resistors can be specified for each bit. o external memory access address output port p2_0/a16 to p2_3/a19 i/o 4-bit i/o port pull-up resistors can be specified for each bit. o external memory access address output port p3_1/psenn i/o 1-bit i/o port pull-up resistors can be specified. o external program memory access read strobe output pin p3_2/rdn o 1-bit output port o external data memory access read strobe output pin p3_3/wrn i/o 1-bit i/o port pull-up resistors can be specified. o external data memory access write strobe output pin p4_0/a0 to p4_7/a7 i/o 8-bit i/o port pull-up resistors can be specified for each bit. o external memory access address output port p6_0/exint0 i external interrupt 0 input pin p6_1/exint1 i external interrupt 1 input pin p6_2/exint2 i external interrupt 2 input pin p6_3/exint3 i/o 4-bit i/o port pull-up resistors can be specified for each bit. i external interrupt 3 input pin p7_6/pwm0out o pwm0 output pin p7_7/pwm1out i/o 2-bit i/o port pull-up resistors can be specified for each bit. o pwm1 output pin p8_0/rxd1 i sio1 receive data input pin p8_1/txd1 o sio1 transmit data output pin p8_2/rxc1 i/o sio1 receive clock i/o pin port p8_3/txc1 i/o 4-bit i/o port pull-up resistors can be specified for each bit. i/o sio1 transmit clock i/o pin
fedl66525-02 oki semiconductor ml66525 family 9/27 description classification symbol type primary function type secondary function p9_0/vbusin i/o 1-bit i/o port pull-up resistors can be specified. i vbus detect external interrupt input pin (5v tolerant input) p10_0/siock3 i/o sio3 transmit-receive clock i/o pin p10_1/sioi3 i sio3 receive data input pin p10_2/sioo3 o sio3 transmit data input pin p10_3/siock4 i/o sio4 (with internal 32-byte fifo) transmit-receive clock i/o pin p10_4/sioo4 o sio4 (with internal 32-byte fifo) transmit data output pin p10_5/sioi4 i/o 6-bit i/o port pull-up resistors can be specified for each bit. i sio4 (with internal 32-byte fifo) receive data output pin p12_0/ai0 to p12_3/ai3 i 4-bit input port i a/d converter analog input port p13_0/exint8 i external interrupt 8 input pin p13_1/exint9 i 2-bit input port i external interrupt 9 input pin p15_0/rxd6 i sio6 receive data input pin p15_1/txd6 o sio6 transmit data output pin p15_2/rxc6 i/o sio6 receive clock i/o pin p15_3/txc6 i/o 4-bit i/o port pull-up resistors can be specified for each bit. i/o sio6 transmit clock i/o pin p20_0/fd0 to p20_7/fd7 i/o 8-bit i/o port pull-up resistors can be specified for each bit. i/o nand flash memory access data i/o port p21_0/frdn i/o o nand flash memory access read strobe output pin p21_1/fwrn i/o o nand flash memory access write strobe output pin p21_2/fcle i/o o nand flash memory access cle strobe output pin p21_3/fale i/o o nand flash memory access ale strobe output pin port p21_4/frb i/o 5-bit i/o port pull-up resistors can be specified for each bit. i nand flash memory access ready/busy input pin
fedl66525-02 oki semiconductor ml66525 family 10/27 classification symbol type description v dd _io i io power supply pin connect all the v dd _io pins.* v dd _core i core power supply pin connect all the v dd _core pins.* vbus i usb power supply pin (vbus input pin) gnd i gnd pin connect all the gnd pins to gnd.* v ref i analog reference voltage pin (connect to the v dd pin when a/d converter is not used.) power supply agnd i analog gnd pin (connect to the gnd pin when a/d converter is not used.) xt0 i sub-clock oscillation input pin connect to a crystal of f = 32.768 khz. xt1n o sub-clock oscillation output pin connect to a crystal of f = 32.768 khz. the clock output is opposite in phase to xt0. osc0 i main clock oscillation input pin connect to a crystal or ceramic oscillator. when an external clock is used, this pin is configured to be clock input. oscillation osc1n o main clock oscillation output pin connect to a crystal or ceramic oscillator. the clock output is opposite in phase to osc0. leave this pin unconnected when an external clock is used. d+ i/o d+ pin d? i/o d? pin usb i/f puctl o external control output pin reset resn i reset input pin nmi i non-maskable interrupt input pin test i test pin connect to the gnd pin for normal operation. v tm i test pin connect to the gnd pin for normal operation. flamod i flash rom programming mode input pin when the flamod pin is set to ?l?, the device enters a programming mode. connect to the v dd _io pin when using as normal operation. others ean i external program memory access input pin when the ea pin is enabled (low level), the internal program memory is masked and the cpu executes the pr ogram code in external program memory through all address space. * connect all v dd _io pins, all v dd _core pins and all gnd pins. if a device has one or more v dd _io, v dd _core, or gnd pins to which the power supply or the ground potential is not connected, the family devic es are not guaranteed to have normal operations.
fedl66525-02 oki semiconductor ml66525 family 11/27 absolute maximum ratings parameter symbol condition rated value unit digital power supply voltage v dd _core v dd _io vbus gnd = agnd = 0 v ta = 25c ?0.3 to +4.6 v other than p9_0 ?0.3 to v dd _io + 0.3 v input voltage v i p9_0 (5 v tolerant input) ?0.3 to +0.6 v output voltage v o ?0.3 to v dd _io + 0.3 v analog reference voltage v ref ?0.3 to +4.6 v analog input voltage v ai ?0.3 to v ref v 100-pin tqfp 680 mw power dissipation p d ta = 70c per package 144-pin lfbga 595 mw storage temperature t stg ? ?50 to +150 c recommended operating conditions parameter symbol condition range unit digital power supply voltage v dd _core v dd _io f osc 24 mhz v dd _core v dd _io 2.4 to 3.6 v analog reference voltage v ref v dd _core v ref 2.4 to 3.6 v analog input voltage v ai ? agnd to v ref v vbus input voltage vbus ? 3.0 to 3.6 v memory hold voltage v ddh f osc = 0 hz 2.0 to 3.6 v usb is used 12, 16, 24 f osc usb is unused 2 to 24 mhz operating frequency f xt ? 32.768 khz ambient temperature ta ? ?30 to +70 c mos load 20 ? p7, p10_0 to p10_2 6 ? fan out n ttl load p0, p1, p2, p3, p4, p6, p8, p9, p10_3 to p10_5, p15, p20, p21 1 ?
fedl66525-02 oki semiconductor ml66525 family 12/27 allowable output current values (v dd _io = 2.4 to 3.6 v, ta = ?30 to +70c) parameter pin symbol min. typ. max. unit ?h? output pin (1 pin) all output pins i oh ? ? ?10 ?h? output pins (sum total) sum total of all output pins i oh ? ? ?70 ?l? output pin (1 pin) all output pins i ol ? ? 10 sum total of p0, p3 sum total of p1, p2, p4 sum total of p6, p7, p8, p9 sum total of p10, p15 35 sum total of p20, p21 70 ?l? output pins (sum total) sum total of all output pins i ol ? ? 160 ma [note] connect all v dd _core and v dd _io pins to the power supply voltage and all gnd pins to the ground voltage. if there is a pin or pins that are not connected to the power supply voltage on ground voltage, the device cannot be guaranteed for normal operation. internal flash rom programming conditions parameter symbol condition rating unit supply voltage v dd _core v dd _io v dd _core v dd _io 2.4 to 3.6 v during read ?30 to +70 c ambient temperature ta during programming +0 to +50 c endurance cep ? 100 cycles blocks size ? ? 128 bytes
fedl66525-02 oki semiconductor ml66525 family 13/27 electrical characteristics dc characteristics 1 (except usb port) (v dd _core = v dd _io = v ref = 2.4 to 3.6 v, gnd = agnd = 0 v, ta = ?30 to +70c) parameter symbol condition min. typ. max. unit ?h? input voltage *1 0.80 v dd ? 5.5 ?h? input voltage v ih ? 0.80 v dd ? v dd + 0.3 ?l? input voltage v il ? ?0.3 ? 0.2v dd i o = ?400 a v dd ? 0.4 ? ? ?h? output voltage *2 i o = ?2.0 ma v dd ? 0.8 ? ? i o = ?200 a v dd ? 0.4 ? ? ?h? output voltage *3 v oh i o = ?1.0 ma v dd ? 0.8 ? ? i o = 3.2 ma ? ? 0.5 ?l? output voltage *2 i o = 5.0 ma ? ? 0.9 i o = 1.6 ma ? ? 0.5 ?l? output voltage *3 v ol i o = 2.5 ma ? ? 0.9 v input leakage current *4, *6 ? ? 1/?1 input current *5 ? ? 1/?90 input current *7 i ih /i il v i = v dd /0 v ? ? 15/?15 a output leakage current *2, *3 i lo v o = v dd /0 v ? ? 10 a pull-up resistance r pull v i = 0 v 40 100 200 k ? input capacitance c i ? 5 ? output capacitance c o f osc = 1 mhz, ta = 25c ? 7 ? pf during a/d operation ? 1.8 5 ma analog reference supply current i ref when a/d is stopped ? ? 5 a v dd = v dd _io * 1. applicable to p9_0 (5 v tolerant input) * 2. applicable to p7 and p10_0 to p10_2 * 3. applicable to p0, p1, p2, p3, p4, p6 , p8, p9, p10_3 to p10_5, p15, p20 and p21 *4. applicable to p12 and p13 *5. applicable to resn and flamod *6. applicable to ean, nmi, and test *7. applicable to osc0
fedl66525-02 oki semiconductor ml66525 family 14/27 supply current ? mask rom version (v dd _core = v dd _io = v ref = 2.4 to 3.6 v, vbus = 3.0 to 3.6 v, gnd = agnd = 0 v, ta = ?30 to +70c) mode symbol condition min. typ. max. unit applicable power supply fosc = 24 mhz, no load ? 28 60 fosc = 24 mhz, dma/media control stopped. no load 18 50 ma cpu operation mode i dd f xt = 32.768 khz, dma/media control stopped. no load *1 ? 100 300 a v dd _core + v dd _io usb operation mode i bus setting of 48 mhz for multiplication selection. no load ? 25 45 ma vbus halt mode i ddh fosc = 24 mhz, dma/media control stopped. no load ? 9 18 ma v dd _core + v dd _io xt is used *2 ? 15 160 stop mode i dds osc is stopped *1 xt is not used *2 ? 10 150 a v dd _core + v dd _io suspend current i susp suspend state osc is stopped, xt is not used * 1 ? 1 100 a vbus the values in the typ. column indicate reference values at 25c and 3.0 v (the vbus currents indicate values at 3.3 v). *1: the temperature condition ranges from ?30 to +50 c *2: the ports used as inputs are at v dd _io or 0 v. other ports are unloaded. ? flash rom version (v dd _core = v dd _io = v ref = 2.4 to 3.6 v, vbus = 3.0 to 3.6 v, gnd = agnd = 0 v, ta = ?30 to +70c) mode symbol condition min. typ. max. unit applicable power supply fosc = 24 mhz, no load ? 28 60 fosc = 24 mhz, dma/media control stopped. no load 18 50 ma cpu operation mode i dd f xt = 32.768 khz, dma/media control stopped. no load *1 ? 100 300 a v dd _core + v dd _io usb operation mode i bus setting of 48 mhz for multiplication selection no load ? 25 45 ma vbus halt mode i ddh fosc = 24 mhz, dma/media control stopped. no load ? 10 20 ma v dd _core + v dd _io xt is used *2 ? 15 160 stop mode i dds osc is stopped *1 xt is not used *2 ? 10 150 a v dd _core + v dd _io suspend current i susp suspend state, d+/d? fixed osc is stopped, xt is not used * 1 ? 1 100 a vbus the values in the typ. column indicate reference values at 25c and 3.0 v (the vbus currents indicate values at 3.3 v). *1: the temperature condition ranges from ?30 to +50 c *2: the ports used as inputs are at v dd _io or 0 v. other ports are unloaded.
fedl66525-02 oki semiconductor ml66525 family 15/27 dc characteristics 2 (usb port) (vbus = 3.0 to 3.6v, ta = ?30 to +70c) parameter symbol condition min. typ. max. unit applicable pin differential input sensitivity v di |(d+) ? (d?)| 0.2 ? ? differential common mode range v cm includes vdi 0.8 ? 2.5 single ended receiver threshold v se 0.8 ? 2.0 v d+, d? 15 k ? to gnd 2.8 ? ? v d+, d? i oh = ?100 a vbus ? 0.2 ? ? ?h? output voltage v oh ioh = ?4 ma 2.4 ? ? v puctl ?l? output voltage v ol 1.5 k ? to 3.6 v ? ? 0.3 v d+, d? v o = vbus/0 v ? ? 10 d+, d? output leakage current i lo v o = vbus/0 v ? ? 10 a puctl
fedl66525-02 oki semiconductor ml66525 family 16/27 ac characteristics (except usb port) (1) external program memory control (v dd _core = v dd _io = v ref = 2.4 to 3.6 v, gnd = agnd = 0 v, ta = ?30 to +70c) parameter symbol condition min. max. unit cycle time t cyc f osc = 24 mhz 41.67 ? clock pulse width (high level) t wh 16.25 ? clock pulse width (low level) t wl 16.25 ? psenn pulse width t pw (2 + 2n)t ? 25 ? psenn pulse delay time t pd ? 55 address setup time t as 2t ? 25 ? address hold time t ah ?10 ? instruction setup time t is 40 ? instruction hold time t ih 0 ? read data access time t acc v dd _core = c l = 50 pf ? (3 + 2n)t ? 50 ns (note) t = t cyc /2 n = 0 to 3 ( n wait cycles inserted) t wh t wl t cyc pc0 to 19 t pw t pd inst0 to 7 t as t ah t acc t is t ih bus timing during no wait cycle time cpuclk psenn a0 to a19 d0 to d7
fedl66525-02 oki semiconductor ml66525 family 17/27 (2) external data memory control (v dd _core = v dd _io = v ref = 2.4 to 3.6 v, gnd = agnd = 0 v, ta = ?30 to +70c) parameter symbol condition min. max. unit cycle time t cyc f osc = 24 mhz 41.67 ? clock pulse width (high level) t wh 16.25 ? clock pulse width (low level) t wl 16.25 ? rdn pulse width t rw (2 + 2n)t ? 25 ? wrn pulse width t ww (2 + 2n)t ? 25 ? rdn pulse delay time t rd ? 55 wrn pulse delay time t wd ? 55 address setup time t as t ? 20 ? address hold time t ah t ? 20 ? read data setup time t rs 40 ? read data hold time t rh 0 ? read data access time t acc ? (3 + 2n)t ? 50 write data setup time t ws 2t ? 30 ? write data hold time t wh c l = 50 pf t ? 6 ? ns (note) t = t cyc /2 n = 0 to 7 ( n wait cycles inserted) t rh t ah t wh t wl t cyc rap0 to 19 t rw t rd din0 to 7 t as t acc t rs cpuclk rdn a0 to a19 d0 to d7 bus timing during no wait cycle time t wh t ah rap0 to 19 t ww t wd dout0 to 7 t as t ws wrn a0 to a19 d0 to d7
fedl66525-02 oki semiconductor ml66525 family 18/27 (3) serial port control 1. serial port 1, 6 (sio1, 6) master mode (clock synchronous serial port) (v dd _core = v dd _io = v ref = 2.4 to 3.6 v, gnd = agnd = 0 v, ta = ?30 to +70c) parameter symbol condition min. max. unit cycle time t cyc f osc = 24 mhz 41.67 ? serial clock cycle time t sckc 4 t cyc ? output data setup time t stmxs 2t ? 10 ? output data hold time t stmxh 5t ? 20 ? input data setup time t srmxs 21 ? input data hold time t srmxh c l = 50 pf 0 ? ns (note) t = t cyc /2 t cyc cpuclk txc/rxc sdout (txd) sdin (rxd) t stmxs t stmxh t sckc t srmxs t srmxh
fedl66525-02 oki semiconductor ml66525 family 19/27 slave mode (clock synchronous serial port) (v dd _core = v dd _io = v ref = 2.4 to 3.6 v, gnd = agnd = 0 v, ta = ?30 to +70c) parameter symbol condition min. max. unit cycle time t cyc f osc = 24 mhz 41.67 ? serial clock cycle time t sckc 4t cyc ? output data setup time t stmxs 2t ? 30 ? output data hold time t stmxh 4t ? 20 ? input data setup time t srmxs 21 ? input data hold time t srmxh c l = 50 pf 7 ? ns (note) t = t cyc /2 txc/rxc sdout (txd) sdin (rxd) t stmxs t stmxh t sckc t srmxs t srmxh t cyc cpuclk
fedl66525-02 oki semiconductor ml66525 family 20/27 2. serial port 4 (sio4) master mode (clock synchronous serial port) (v dd _core = v dd _io = v ref = 2.4 to 3.6 v, gnd = agnd = 0 v, ta = ?30 to +70c) parameter symbol condition min. max. unit cycle time t cyc f osc = 24 mhz 41.67 ? serial clock cycle time t sckc 400 ? output data setup time t stmxs 190 ? output data hold time t stmxh 130 ? input data setup time t srmxs 21 ? input data hold time t srmxh c l = 50 pf 0 ? ns t cyc cpuclk txc/rxc sdout (txd) sdin (rxd) t stmxs t stmxh t sckc t srmxs t srmxh
fedl66525-02 oki semiconductor ml66525 family 21/27 slave mode (clock synchronous serial port) (v dd _core = v dd _io = v ref = 2.4 to 3.6 v, gnd = agnd = 0 v, ta = ?30 to +70c) parameter symbol condition min. max. unit cycle time t cyc f osc = 24 mhz 41.67 ? serial clock cycle time t sckc 400 ? output data setup time t stmxs 70 ? output data hold time t stmxh 180 ? input data setup time t srmxs 21 ? input data hold time t srmxh c l = 50 pf 7 ? ns txc/rxc sdout (txd) sdin (rxd) t stmxs t stmxh t sckc t srmxs t srmxh t cyc cpuclk measurement points for ac timi ng (except the serial port) measurement points for ac timing (the serial port) v dd _io 0 v 0.16v dd _io 0.44v dd _io 0.16v dd _io 0.44v dd _io v dd _io 0 v 0.2v dd _io 0.8v dd _io 0.2v dd _io 0.8v dd _io
fedl66525-02 oki semiconductor ml66525 family 22/27 a/d converter characteristics (ta = ?30 to +70c, v ref = 2.4 to 3.6 v, agnd = gnd = 0 v) parameter symbol condition min. typ. max. unit resolution n ? 10 ? bit linearity error e l ? ? 3 differential linearity error e d ? ? 2 zero scale error e zs ? ? +3 full-scale error e fs refer to measurement circuit 1 analog input source impedance r i 5 k ? ? ? ?3 cross talk e ct refer to measurement circuit 2 ? ? 1 lsb conversion time t conv set according to adtm set data 16 ? 3906.3 s/ch v ref reference voltage v dd _io gnd ? + analog input r i ai0 to ai3 c i 0.1 f 47 f + 0.1 f 47 f + +3 v 0 v agnd r i (impedance of analog input source) 5 k ? c i ? 0.1 f measurement circuit 1
fedl66525-02 oki semiconductor ml66525 family 23/27 ? + analog input 5 k ? 0.1 f ai0 ai1 ai3 cross talk is the difference between the a/d conversion results when the same analog input is applied to ai0 through ai3 and the a/d conversion results of the circuit to the left. to v ref or agnd measurement circuit 2 definition of terminology 1. resolution resolution is the value of minimum discernible analog input. with 10 bits, since 2 10 = 1024, resolution of (v ref ? agnd) 1024 is possible. 2. linearity error linearity error is the difference between ideal conve rsion characteristics and actual conversion characteristics of a 10-bit a/d converter (not including quantization error). ideal conversion characteristics can be obtained by dividing the voltage between v ref and agnd into 1024 equal steps. 3. differential linearity error differential linearity error indicates the smoothness of c onversion characteristics. id eally, the range of analog input voltage that corresponds to 1 converted bit of digital output is 1lsb = (v ref ? agnd) 1024. differential error is the difference between this ideal bit size and bit size of an arbitr ary point in the conversion range. 4. zero scale error zero scale error is the difference between ideal conversion characteristics and actual conversion characteristics at the point where the digital output changes from 000h to 001h. 5. full-scale error full-scale error is the difference be tween ideal conversion characteristic s and actual conversion characteristics at the point where the digital output changes from 3feh to 3ffh.
fedl66525-02 oki semiconductor ml66525 family 24/27 package dimensions notes for mounting the surface mount type packages the surface mount type packages ar e very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform re flow mounting, contact oki?s responsible sales person on the product name, package name, pin number, package code a nd desired mounting conditions (reflow method, temperature and times). tqfp100-p-1414-0.50-k mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5m) package weight (g) 0.55 typ. 5 rev. no./last revised 4/oct. 28, 1996 (unit: mm)
fedl66525-02 oki semiconductor ml66525 family 25/27 package dimensions notes for mounting the surface mount type packages the surface mount type packages ar e very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform re flow mounting, contact oki?s responsible sales person on the product name, package name, pin number, package code a nd desired mounting conditions (reflow method, temperature and times). p-lfbga144- 1111-0.80 package material epoxy resin ball material sn/pb package weight (g) 0.30 typ. 5 rev. no./last revised 1/aug. 25, 1999 (nit mm)
fedl66525-02 oki semiconductor ml66525 family 26/27 revision history page document no. date previous edition current edition description pedl66525-01 oct. 2000 ? ? preliminary edition 1 pedl66525-02 mar. 2001 ? ? - modified contents of p3_2 and p3_3 in the table on page 8. - added contents of p9_0 in the table on page 9. - modified contents of puctl in the table on page 10. - partially added contents of ?absolute maximum ratings?. - partially added contents of ?recommended operating conditions?. - partially added contents of ?allowable output current values?. - partially added contents of ?internal flash rom programming conditions?. - partially added contents of ?electrical characteristics?. fedl66525-01 oct. 2001 ? ? - changed the name from ml66525 to ml66525a. - changed the name from ml66q525 to ml66q525a. - modified supply current values for ml66q525 on page 14. - modified contents of the table on page 21. fedl66525-02 jul. 19, 2002 ? ? - changed the name from ml66525a to ml66525b. - changed the name from ml66q525a to ml66q525b.
fedl66525-02 oki semiconductor ml66525 family 27/27 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circu it, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improp er installation, repair, alteration or accident, improp er handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third part y?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communicati on equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for us e in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and auto motive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2002 oki electric industry co., ltd.

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